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中文题名:

 FPGA与PC间基于PCIe和千兆以太网的通信设计    

姓名:

 温春江    

学号:

 1202121122    

保密级别:

 公开    

论文语种:

 chi    

学科代码:

 0810    

学科名称:

 信息与通信工程    

学校:

 西安电子科技大学    

院系:

 电子工程学院    

专业:

 信号与信息处理    

第一导师姓名:

 唐禹    

第一导师单位:

 西安电子科技大学    

完成日期:

 2014-12-09    

答辩日期:

 2014-12-09    

外文题名:

 Design of Transmission Between FPGA and PC Based on PCIe and Gigabit Ethernet    

中文关键词:

 高速接口 ; PCIe ; WinDriver ; 千兆以太网口 ; Winpcap    

中文摘要:
随着系统性能、功能和带宽的提高,高速数据采集与记录以及其他数据处理的数据吞吐量都日益增长。因此通过研究发展新的高速接口技术来解决带宽限制和高速传输这些关键问题是一种必然趋势和迫切的需求。FPGA已发展成为实现数字系统的主流平台之一,广泛应用于信号处理及通信等各个领域。FPGA在信号处理时可并行运行,处理速度快,但不适合实现高精度复杂的运算处理。而PC计算机具备相当强大的计算和数据处理能力,所以通常情况下会将需要进行高精度复杂的计算交由计算机负责处理。这就涉及到FPGA与PC间进行大量数据的传输问题,因此构建PC机与FPGA的高速数据传输系统成为当前的研究趋势。本文根据当前研究趋势和实际科研项目要求,对PCIe和千兆以太网进行了深入研究,并设计了PCIe DMA数据传输系统和千兆以太网数据传输系统来实现FPGA与PC机之间的数据通信。本文的具体工作如下:1. 深入研究PCIe和千兆以太网,了解PCIe和千兆以太网的技术优势,具体分析PCIe和千兆以太网的传输协议,详细说明PCIe TLP数据包格式和以太网标准数据帧格式。2. 完成PCIe DMA数据传输系统设计。设计方案主要包括两大部分,分别是FPGA端Verilog逻辑模块开发以及PC端的驱动和C应用程序开发。FPGA端基于PCIe IP Core完成了发送接收引擎模块、寄存器读写控制模块和FIFO读写控制模块的设计。定义了相应模块的接口,并分析了数据传输的时序。PC端采用WinDriver进行PCIe的驱动开发,并根据WinDriver提供的驱动API函数完成C应用程序的设计。3. 完成千兆以太网数据传输系统设计。设计方案也主要包括两大部分,分别是FPGA端Verilog逻辑模块开发以及PC端Winpcap应用程序开发。FPGA端基于嵌入式三态以太网MAC IP Core,设计了发送接收引擎模块、FIFO读写控制模块和物理接口模块。定义了相应模块的接口,并分析了数据传输经过LocalLink接口和Client用户接口上的传输时序。PC端采用Winpcap提供的网络编程完成了C应用程序的设计,实现了捕获FPGA端发送的数据包以及发送原始数据包至FPGA端的功能。4. PCIe DMA数据传输系统和千兆以太网数据传输系统在Xilinx ML507开发板上进行了性能测试。记录FPGA与PC间进行读写测试的结果,验证这两个系统的可用性和稳定性,最后分析了影响系统传输速率的原因以及系统目前仍存在的不足。本文设计的PCIe DMA数据传输系统和千兆以太网数据传输系统基本实现了FPGA与PC间大量数据的快速传输,对后续科研做出了一定的贡献。
外文摘要:
With the improvement of system performance, function and bandwidth, data throughput of high speed data collection and other data processing are increasing. Therefor the usage of new high speed interface technology to solve the bottleneck problem about bandwidth limitation and high speed transmission becomes increasingly important. FPGA has developed to be one of the main platform on digital system and widely used in many fields, such as signal processing and communication. FPGA can realize parallel processing and obtain a high speed, but FPGA is not directly appropriate for high-precision and complex operation while PC has powerful calculating and data processing capacity. Consequently, the high-precision and complex operation are accomplished by PC generally, which results in the transmission between FPGA and PC. So building a high speed data transmission system between FPGA and PC becomes a research tendency. According to the current research tendency and the actually requirement, PCIe DMA data transmission system and Gigabit Ethernet data transmission system are designed in this paper with deep research into PCIe and Gigabit Ethernet. The following works have been done in this paper:1. PCIe and Gigabit Ethernet has been deeply researched including technological superiority, the protocol and data frame form.2. PCIe DMA data transmission system has been designed. The system consists of two components, one of which is the logic module development with verilog language on FPGA and the other is the C application program development with WinDriver on PC. According to PCIe IP Core, TX and RX Engine module, the access controlling modules of register and FIFO have been realized on FPGA side. Then the interfaces of the modules above have been defined, and the data transmission timming has been analyzed. The PCIe driver has been developed by WinDriver, and the C application program has been designed according to WinDriver API functions.3. Gigabit Ethernet data transmission system has been designed. The system consists of two components, one of which is the logic module development with verilog language on FPGA and the other is the application development with Winpcap on PC. Based on the Embedded Tri-Mode Ethernet MAC wrapper on FPGA, the TX and RX Engine module, the FIFO controlling module and the physical interface module have been completed. The interfaces of the three modules above have been defined, and the data transmission timming on locallink interfaces and client interfaces has been analyzed. Using the network programming provided by Winpcap on the PC, the C application program has been finished, which realize to capture data packets from FPGA and to send data packets to FPGA.4. PCIe DMA data transmission system and Gigabit Ethernet data transmission system have passed the performance testing on Xilinx ML507 development board. According to the transmission results, the availability and stability of the two systems have been verified and analyzed.Massive data transmission between FPGA and PC has basically realized based on PCIe DMA data transmission system and Gigabit Ethernet data transmission system, which is made a certain contribution on the future relevent research.
中图分类号:

 11    

馆藏号:

 11-24666    

开放日期:

 2015-09-13    

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